(1) Field of the Invention
This invention relates to a clock switching circuit for switching and outputting a plurality of input clock signals having different frequencies and, in particular, to a clock switching circuit usable regardless of the frequency ratio of input clock signals.
(2) Description of the Related Art
Recently large-scale integration (LSI) systems are designed to dynamically change an operating clock frequency because of a strong demand of low current consumption. To meet this demand, they operate with a lower-frequency clock signal during slow operation such as standby, for example. Each of the LSI systems containing phase-locked loops (PLL) requires to dynamically switch between an output clock signal of the PLL and a different clock signal. As clock signals to be switched, asynchronous clock signals having different frequencies and different periods are used in many cases.
To select one clock signal out of two, conventional LSI systems use simple selectors. These simple selectors, however, have a problem that asynchronous input clock signals produce an output clock signal having an irregular pulse width called a hazard, thereby causing circuit malfunction.
To solve this problem, such asynchronous-clock switching circuit as to prevent hazards has been proposed.
FIG. 4 shows an example of a construction of a conventional clock switching circuit.
This clock switching circuit of FIG. 4 switches between two asynchronous input clock signals CLKIN_A and CLKIN_B based on a select signal SEL and outputs one signal as an output clock signal CLKOUT. An H-level select signal SEL selects the input clock signal CLKIN_A while an L-level select signal SEL selects the input clock signal CLKIN_B.
This clock switching circuit is composed of a first flip-flop (FF) group 110, a second FF group 120, and an AND gate 109. The first FF group 110 is provided with two-stage FFs 111 and 112 which both operate according to one input clock signal CLKIN_A, and disables the output of this signal CLKIN_A while the signal is not selected. Similarly, the second FF group 120 is provided with two-stage FFs 121 and 122 which both operate according to the other input clock signal CLKIN_B, and disables the output of this signal CLKIN_B in case where the signal is not selected. The AND gate 109 receives output signals CLK_A and CLK_B from the first and second FF groups 110 and 120 and outputs the output clock signal CLKOUT.
The first FF group 110 is composed of the two-stage FFs 111 and 112, inverters 101 and 102, and OR gates 103 and 104. The FF 111 takes in the select signal SEL on the rising edge of the input clock signal CLKIN_A. The FF 112 takes in an output signal SEL_A of the FF 111 on the rising edge of the input clock signal CLKIN_A.
The inverter 101 inverts and enters the output signal SEL_A of the FF 111 to one input terminal of the OR gate 103. The inverter 102 inverts and enters an output signal SEL_AA of the FF 112 to the other input terminal of the OR gate 103. An output signal (clock mask signal MASK_A) of the OR gate 103 and the input clock signal CLKIN_A are entered to the input terminals of the OR gate 104. An output signal CLK_A of the OR gate 104 is entered to one input terminal of the AND gate 109.
Similarly, the second FF group 120 is composed of the two-stage FFs 121 and 122, inverters 105 and 106, OR gates 107 and 108. The FF 121 takes in the inverted signal nSEL of the select signal SEL on the rising edge of the input clock signal CLKIN_B. The FF 122 takes in an output signal nSEL_B of the FF 121 on the rising edge of the input clock signal CLKIN_B.
The inverter 105 inverts and enters the output signal nSEL_B of the FF 121 to one input terminal of the OR gate 107. The inverter 106 inverts and enters an output signal nSEL_BB of the FF 122 to the other input terminal of the OR gate 107. In the input terminals of the OR gate 108, an output signal (clock mask signal MASK_B) of the OR gate 107 and the input clock signal CLKIN_B are entered. An output signal CLK_B of the OR gate 108 is entered to the other input terminal of the AND gate 109.
FIG. 5 shows a first time chart showing signal output timing of each unit in the above clock switching circuit.
In the first FF group 110, the input clock signal CLKIN_A is fixed at H level and masked in the OR gate 104 depending on the clock mask signal MASK_A output from the OR gate 103. The clock mask signal MASK_A starts to rise at the first rising time (T501) of the input clock signal CLKIN_A after the select signal SEL becomes L level. The clock mask signal MASK_A starts to fall at the second rising time (T504) of the input clock signal CLKIN_A after the select signal SEL becomes H level.
Similarly, in the second FF group 120, the input clock signal CLKIN_B is fixed at H level and masked in the OR gate 108 depending on the clock mask signal MASK_B output from the OR gate 107. The clock mask signal MASK_B starts to rise at the first rising time (T503) of the input clock signal CLKIN_B after the select signal SEL becomes H level. The clock signal MASK_B starts to fall at the second rising time (T502) of the input clock signal CLKIN_B after the select signal SEL becomes L level.
As described above, in each FF group, two-stage FFs which both operate according to the same input clock signal are connected in series, and masking starts based on an output signal of the first FF and the masking ends based on an output signal of the second FF. Accordingly, at the time of switching between input clock signals, there exist periods during which the clock mask signals MASK_A and MASK_B have both H level, like periods between the times T501 and T502 and the times T503 and T504 in FIG. 5. Therefore, the two input clock signals are avoided from being conflicted and output, thus preventing hazards.
In the circuit configuration of FIG. 4, the input clock signals are fixed at H level and masked. As an alternative way, the input clock signals can be fixed at L level and masked, provided that AND gates are arranged in place of gate circuits in each FF group and an OR gate is arranged in place of a gate circuit of the output stage.
The above clock switching circuit, however, has a problem that occurrence of hazards cannot be prevented if input clock signals have big difference in frequency, specifically, if one frequency is twice or more as fast as the other one.
FIG. 6 is a second time chart showing signal output timing of each unit of the above clock switching circuit.
FIG. 6 shows an example of signal output timing in a case where the frequency of one input clock signal CLKIN_B is twice or more as fast as that of the other input clock signal CLKIN_A in the above clock switching circuit. In this FIG. 6, when the slow input clock signal CLKIN_A is switched to the fast input clock signal CLKIN_B based on a select signal SEL, a clock mask signal MASK_B changes to L level at time T601 before time T602 at which the clock mask signal MASK_A becomes H level. Therefore, during the times T601 to T602, the clock mask signals MASK_A and MASK_B have both L level, resulting in producing a hazard as shown in a part C in this figure.
This problem can be avoided by arranging more FFs in the FF group 110 for disabling the output of the slow input clock signal CLKIN_A, for example. With similar configuration, considering a communication interface with a hot plug function, a clock switching circuit has been proposed, which prevents occurrence of hazards at a time of switching between a fast input clock signal and a slow input clock signal output from a built-in PLL (for example, refer to Japanese Unexamined Patent Publication No. 2001-209453 (sections [0026] to [0040], FIG. 5)).
As a conventional related technical art, an asynchronous-clock switching circuit has been proposed. This circuit is provided with: a select signal generating part for controlling a selector based on a select signal, the selector selecting and sending clock signals of systems 0 and 1; and an inhibition area setting part for controlling a reset signal corresponding to each system. The circuit is designed such that the inhibition area setting part sets a hazard inhibition area according to a detection signal of a clock break of each system and performs the clock switching (for example, refer to Japanese Unexamined Patent Publication No. 6-209309 (sections [0019] to [0027], FIG. 2)).